hdlbits_Module_shift

Module_shift

You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.

The module provided to you is: module my_dff ( input clk, input d, output q );

Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.

Module_shift

solution

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module top_module ( input clk, input d, output q );
wire q1,q2;
my_dff dffins1(clk, d, q1);
my_dff dffins2(clk, q1, q2);
my_dff dffins3(clk, q2, q);

endmodule


hdlbits_Module_shift
http://456-xiao.github.io/2024/08/06/hdlbits-Module-shift/
作者
xyh
发布于
2024年8月6日
许可协议